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Altera_Forum
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10 years ago

Error (10822)

Hello, please help me with this problem. Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity encoder is port( clk:in std_logic; A:in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You are using both rising edge and falling edge in the same process. Don't do that. Synchronous designs are designed to run on one edge, typically rising edge. There are only certain specialized cases like DDR where both edges are to be used. Those situations are to simply clock in data, not implement some logic function as you are doing.

Kevin Jennings