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Altera_Forum
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12 years ago

Error (10818) What is wrong ??

Hi I'm try write this code. I don't now what is to change:confused:

Quartus log:

Error (10818): Can't infer register for "CLK_OUT" at PISO_SPI_LCD.vhd(40) because it does not hold its value outside the clock edge

Error (10822): HDL error at PISO_SPI_LCD.vhd(40): couldn't implement registers for assignments on this clock edge

library ieee;use ieee.std_logic_1164.all;
--use ieee.std_logic;
--use ieee.std_match;
entity PISO_SPI_LCD is
generic(DATA_IN_LENGTH: integer :=9);
port(
        DATA_IN_XBIT     : IN bit_vector((DATA_IN_LENGTH-1) downto 0);
        CLK_IN    : IN bit;
        NRESET    : IN bit;
        
        DATA_OUT    : OUT bit;
        CLK_OUT    : OUT bit;
        READY_OUT: OUT bit);    -- 1= ready to send new data 0= is sending
end PISO_SPI_LCD;
architecture first of PISO_SPI_LCD is
signal send_is_running_status : bit :='0';    -- 1= runn 0= idle
signal new_data_to_send_status : bit :='0';
signal DATA_IN_TMP : bit_vector ((DATA_IN_LENGTH-1) downto 0);
signal DATA_IN_TMP2 : bit_vector ((DATA_IN_LENGTH-1) downto 0);
signal CLK_OUT_TMP : bit :='0';
signal COUNTER : integer range 0 to 16 := 0;
begin
init: process (DATA_IN_XBIT) is 
begin
    if(send_is_running_status = '0')then
        DATA_IN_TMP2 <= DATA_IN_XBIT;    -- copy data to burref when sennding is disable
        send_is_running_status <='1';
    end if;
end process init;
    
set_data: process (NRESET,CLK_IN) is
begin
    if(NRESET'event and NRESET = '0') then
        DATA_OUT <= '0';
    elsif(CLK_IN ='0')then -- if falling clk
        if(new_data_to_send_status ='0')then
            DATA_IN_TMP <= DATA_IN_TMP2;
            new_data_to_send_status <='1'; -- enable start to transfet data
        elsif(new_data_to_send_status ='1') then
            DATA_OUT <= DATA_IN_TMP(DATA_IN_LENGTH-1); -- get MSB bits and send to output
            DATA_IN_TMP <= DATA_IN_TMP(DATA_IN_LENGTH-2 downto 0 ) & '0'; -- shift left data
            CLK_OUT <='0';
        end if;
40    elsif(CLK_IN ='1') then -- if rising clk -- line 40
        if(new_data_to_send_status <='1')then
        CLK_OUT <='1';
        end if;
    end if;
end process set_data;
end architecture first;

This is my first post, if something is wrong:oops: please write..

Please help and tips.

Thank you.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    First you can't use both clock edges on a register, either edge but not both.

    another error:

    --- Quote Start ---

    init: process (DATA_IN_XBIT) is

    begin

    if(send_is_running_status = '0')then

    DATA_IN_TMP2 <= DATA_IN_XBIT; -- copy data to burref when sennding is disable

    send_is_running_status <='1';

    end if;

    end process init;

    --- Quote End ---

    your send_is_running_status will just glitch up and down with tiny delay of path.

    there is also syntax error at

    new_data_to_send_status <= '1' which should be =