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Altera_Forum
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7 years ago

Error (10759) when compile boardtest.cl kernel

when i run to compile boardtest.cl kernel, have the bellow error : error (10759) the verilog hdl error at boardtest_system.v :object kclk_finish declared in a list of port decralation cannot be rede...
Altera_Forum's avatar
Altera_Forum
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7 years ago

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Info (125068): Revision "top" was previously opened in Quartus II software version 16.0.2. Created Quartus Prime Default Settings File E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 16.0.2.

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It seems the BSP you are using is not compatible with your version of Quartus. Check your board manufacturer's instructions as to which version of Quartus you should be using.