error 10559 VHDL

The rising edge function requires the input to be a signal because it uses various attributes that only exist on a signal. The problem is that Z is a constant.

But I don't really understand this function. The variables will be re initialised every time the function is called, so it will only ever return 0 or 1. Why are you using a function and not a process?

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Hi,

I was wondering if anyone can shed some light on this error that I managed to obtain.

Error (10559): VHDL Subprogram Call error at user_functions.vhd(100): actual for formal parameter "s" must be a "signal"

This is the chunk of code where the error occurs it is a function designed to count the rising edges on a signal. and this is to be implemented in main body of the code 4 times, as I need a counter for four signals.

FUNCTION COUNTER(Z:std_logic; Reset:std_logic) RETURN natural IS

variable count: natural range 0 to 65535;

variable Q: natural range 0 to 65535;

begin

(line 100) if (rising_edge(Z)) then

if Reset = '0' then

count := 0;

else

count := count + 1;

end if;

end if;

Return count;

end;

END user_functions;

Is it that I cannot use a subprogram within a new function description?

Let me know if you require more information.

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Hi ,

I dont where "s" is defined as a signal for variable :

actual for formal parameter "s" must be a "signal"

Also this should be put in a process , functions are mostly used for mathematical or data conversion tasks .

Would help if i could see how is it called within the main architecture .

Regards ,

Ahmed Asim Ghouri

Embedded Strings inc

Website : www.emstrings.com

Email : support@emstrings.com

To elaborate a bit about the problem, the only case where a register in a subprogram can be synthesized is a construct like below. But it won't work for a counter because the out port can't be read inside the procedure.

procedure ff (
  signal clk: in std_logic;
  signal d : in std_logic;	
  signal q : out std_logic) is
begin
  if rising_edge(clk) then
    q <= d;
  end if;	 
end;