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Altera_Forum's avatar
Altera_Forum
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9 years ago

Error (10500) for storing coordinates pixel of a binary image

Hi. I am novice working with FPGAS, I want to add all the coordinates pixels of an image, and each pixel is composed by a coordinate pair (i,j) But I have a mistake when I compile my code.

I previously saved the mif file into ROM. My binary image is 256x256 I really need the help.:cry:

Thanks!

[SUP]library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity covariance is

end entity;

architecture behavioral of covariance is

component ROM1 IS -- Into this memory is the binary image to analyse

PORT

(

address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

clock : IN STD_LOGIC := '1';

q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

 );

END component;

type Mat1 is array (0 to 1, 0 to 0) of integer range 0 to 256; -- pixel

type Mat2 is array (0 to 1, 0 to 0) of integer range 0 to 65536; -- pixel's accumulator

signal clk, done: std_logic :='0';

signal add_rom : std_logic_vector(15 downto 0):= (others => '0');

signal out_im : std_logic;

signal pixel: Mat1;

signal acum : Mat2;

--pixel<=(0,0);

acum<=(0,0);

BEGIN

process (clk)

begin

if (falling_edge(clk))then -- If there is CLK

if(done='0')then --

for i in 0 to 256 loop

for j in 0 to 256 loop

if out_im = '0' then -- Compare it with zero the first pixel

add_rom <= add_rom + "0000000000000001"; --

pixel <= (i,j);

acum <= acum + pixel;

end if;

end loop;

end loop;

end if;

end if;

end process;

END behavioral;[/SUP]

And the error that appears after compilation is

[SUP]Info: *******************************************************************

Info: Running Quartus II 64-Bit Analysis & Synthesis

Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition

Info: Processing started: Wed Aug 24 00:53:34 2016

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off covariance -c covariance

Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.

Error (10500): VHDL syntax error at covariance.vhd(30) near text "acum"; expecting "begin", or a declaration statement

Info (12021): Found 0 design units, including 0 entities, in source file covariance.vhd

Info (12021): Found 2 design units, including 1 entities, in source file rom1.vhd

Info (12022): Found design unit 1: rom1-SYN

Info (12023): Found entity 1: ROM1

Info (12021): Found 2 design units, including 1 entities, in source file contador.vhd

Info (12022): Found design unit 1: contador-Behavioral

Info (12023): Found entity 1: contador

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: Peak virtual memory: 477 megabytes

Error: Processing ended: Wed Aug 24 00:53:35 2016

Error: Elapsed time: 00:00:01

Error: Total CPU time (on all processors): 00:00:01[/SUP]

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    You accum assigned before the begin. It must be assigned inside the begin - end pair. before the begin is for declarations only.

    But there are several other issues here:

    Why have you declared the mat1 and mat2 types as 2d array with really only 1 dimension? why not just write:

    type Mat1 is array (0 to 1) of integer range 0 to 256;

    This allows acum to be assigned as you did:

    acum <= (0,0);

    with you current declaration:

    type Mat1 is array (0 to 1, 0 to 0) of integer range 0 to 256;

    you need to assign acum like this:

    acum <= ( (0), (0) );

    Next - what do you expect the for loops to do in your code? loops are unrolled when the code is compiled. Apart from the fact that out_im is currently unconnected, your signals only get the last value assigned to then, so add_rom will always be +1, pixel will always be (256, 256) and acum cannot assigned because you didnt define a + function for your Mat2 type.

    This looks rather like a software program, not HDL.