Error 10346: Formal port or parameter "write" must have a actual or default value

usually this error happens when the component has a generic clause:

entity blablabla...

generic( width := 8 ) -- default value

port(

...

Please, post the code better understanding of the error.

Thanks for your kindly reply.

But the "write" is a 1-bit port! this port doesn't have any parameter defination in the design!

As the design shows bellow:

component syncram

generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;

testen : integer := 0);

port (

clk : in std_ulogic;

address : in std_logic_vector((abits -1) downto 0);

datain : in std_logic_vector((dbits -1) downto 0);

dataout : out std_logic_vector((dbits -1) downto 0);

enable : in std_ulogic;

write : in std_ulogic;

testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none);

end component;

When you instantiate the component. Did you connect that port to any signal?

In same line of code you have.

toto_unit : syncram....

port map(....

write => some_signal, -- did you place this connection?

yes, they are some others signals need to be assign by the write.

For example:

xwrite <= write;

Does this cause the error?

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It sounds like you forgot to connect the write port. All ports of mode in must be connected to something, even if it is '0' or '1'. They cannot be left open.

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Problem solved, Thanks!