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jcl2000's avatar
jcl2000
Icon for New Contributor rankNew Contributor
5 years ago
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Error (10327): VHDL error at QA4.vhd(48): can't determine definition of operator "">""

Not sure why i'm getting this error, any help would be appreciated. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; Entity Radar is port(rin : in STD_LOGIC_VECTOR(7 downto...
  • RichardT_altera's avatar
    RichardT_altera
    5 years ago

    I am not a VHDL expert but I believe that the less than ">" operator has been used to compare two type of value: std_logic_vector and integer.

    Greater than and less than are relational operators, while using relational operators is that the two numbers being compared must be of the same 'type'. An integer cannot be compared to a std_logic_vector type value.

    From what I get from another case:

    https://community.intel.com/t5/Intel-Quartus-Prime-Software/Error-10327-Can-t-determine-definition-of-operator-quot-quot/td-p/61149

    You can use explicit numeric types SIGNED or UNSIGNED. Alternatively you can use a library that treats all std_logic_vector as SIGNED or UNSIGNED type: IEEE.STD_LOGIC_SIGNED respectively IEEE.STD_LOGIC_UNSIGNED.

    I hope it helps.

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

I am not a VHDL expert but I believe that the less than ">" operator has been used to compare two type of value: std_logic_vector and integer.

Greater than and less than are relational operators, while using relational operators is that the two numbers being compared must be of the same 'type'. An integer cannot be compared to a std_logic_vector type value.

From what I get from another case:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Error-10327-Can-t-determine-definition-of-operator-quot-quot/td-p/61149

You can use explicit numeric types SIGNED or UNSIGNED. Alternatively you can use a library that treats all std_logic_vector as SIGNED or UNSIGNED type: IEEE.STD_LOGIC_SIGNED respectively IEEE.STD_LOGIC_UNSIGNED.

I hope it helps.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    I believed that I have answered your question and I yet to receive any response from you to the previous question/reply/answer that I have provided.
    With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.