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CSoti
New Contributor
7 years agoError (10232): Verilog HDL error : index 22 cannot fall outside the declared range [21:0] for vector "address"
I am using Quartus Prime Lite Edition 18.1 to generate a system that includes a Platform designer system with Avalon MM Master-Slave interface. Every time I use more than 2 slaves I get the following...
CSoti
New Contributor
7 years agoThe above solution did not apply to my project. However, I removed a peripheral and with some adjustments in the avalon mm wrapper the project passes synthesis. For the time being the project is stable. It remains to be seen if it will remain so when I add the rest of the peripherals again.