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Honored Contributor
Honored Contributorerror 10161 when importing vhdl packages to system verilog
Hi, My toplevel design is in system verilog, I import a VHDL package with record type, quartus errors with "Error (10161): Verilog HDL error at dummy_sysver.sv(3): object "dummy_vhd_pkg" is not...
Altera_ForumHonored Contributor
Honored ContributorThanks Tricky,
In the end I had to modify the VHDL toplevel record port into various SLV port.
