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Altera_Forum
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9 years ago

error 10161 when importing vhdl packages to system verilog

Hi, My toplevel design is in system verilog, I import a VHDL package with record type, quartus errors with "Error (10161): Verilog HDL error at dummy_sysver.sv(3): object "dummy_vhd_pkg" is not...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks Tricky,

In the end I had to modify the VHDL toplevel record port into various SLV port.