Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Error (10028): Can't resolve multiple constant drivers for net <name> at <??>

All, Here is one of my Verilog trial-learning code: ============================================================== // Verilog learning example module SRAM_Read_Write_Sync ( nrst, Writeclk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

if you have a clock, the the only thing that should be in the sensitivity list (inside the brackets of the always) are the Readclk and nrst. You only care what happens on the clock edge, hence you dont want anything else. If you are trying to do logic with the clock, you are going to fail as this wont be possible in an FPGA. at the top level you should have: 


always @(posedge Readclk or negedge nrst) begin
  if(~nrst) begin
    // asynchronous reset goes here
  else begin
    // this is for synchronous logic
  end
  // NOTHING ELSE HERE
end