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Altera_Forum
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Honored ContributorEncoder for dsd audio stream in SDIF-3 format, VHDL - help a newbie
Hello folks, I'm a newbie in VHDL programming. I'm trying to achieve SDIF-3 encoding from a dsd datastream coming off from an A-D conversion chip. The dsd stream from the chip features two...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Thanks a lot! One thing that bugs me is that SDIF-3 seems to be the inverted of Manchester. From this paper (https://www.ijarcce.com/upload/2016/april-16/ijarcce%20114.pdf) the simplest way to implement a Manchester encoder is to XOR Din and Clkin to obtain '01' for a '1' from source, and '10' for a '0' source. Since sdif3 needs '10' for a '1' and '01' for a '0', will a simple replacement of XOR with an xnor do the trick? What are your thoughts? --- Quote End --- Beware of using combinatorial logic where the clock used to generate the other signals is used as a signal too; you may/will get issues with the small delays between the clock and the generated input signals which may/will result in an output with glitches. Using a double frequency clock to generate the output signal excludes that possible issue alltogether.
