Efficient State Machine Design

I think you will find that by default the Quartus tools will analyze your state machine, discard the current encoding (one-hot, binary, gray, etc), and then re-encode the state machine during the implementation phase, which for most state machines will end up being one-hot encoded. This is usually the most space and time efficient encoding given FPGA cell architecture. So what you write in your HDL (encoding-wise) really does not matter.