Forum Discussion
Altera_Forum
Honored Contributor
12 years agoOn some research, it seems the COMMAND register of the endpoint , bit 1 needs to be set for the endpoint to respond to memory requests .
I have no device driver active at this time , so that may make sense. I am writing a Lauterbach .cmm script first to exercise the endpoint before getting a simple device driver going ( Linux ), to work with our exerciser running on Linux. I am planning to review the simple device drivers for Altera PCIe endpoints with MM to see what basic device configuration takes place during the pcie_init.