New ContributorHi,
I have generated the eCPRI IP. When i try to compile the IP in the Intel Quartus v21.4 software, the compilation is not happening.
After couple of hrs,
It reports "Verilog or VHDL error" : cannot open verilog file 'ipcore/ip_ecpri/ecpri_141/synth/*.sv'.
At the same time, the Compile process status is still 0%.
Please provide your support to understand this.
Note: I have attached the screen shot.
Thank you,
Ananth
Frequent ContributorHi Ananthraj,
Can you please share your project to replicate the issue.
Have you connected the ports?
Thank you
Kshitij Goel
Frequent ContributorHi,
Also, please try with eCPRI example design https://www.intel.com/content/www/us/en/docs/programmable/683837/21-2-1-3-1/quick-start-guide.html
Thank you
Kshitij Goel
Frequent ContributorHi,
Also, It seems to be path issue. Please check your path.
Thank you
Kshitij Goel
Frequent ContributorHi,
As We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Thank you.
