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Altera_Forum
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8 years ago

Easiest Testbench for my VHDL code (multiplication)

Hello there. Is there somebody who can make testbench from my vhdl code? It is multiplication of 2 integers, which are n-1 downto 0.. n=16. Thanks a lot.. 

library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity MultExample is
Generic ( n  : natural := 16);
Port (A,B : in std_logic_vector(n-1 downto 0);        
			Q : out std_logic_vector(n*2-1 downto 0);
		
			 
end MultExample;
architecture Behavioral of MultExample is
BEGIN
	Q <= std_logic_vector(signed(A) * signed(B));
end architecture Behavioral;

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    I will try to send there both codes..

    nasobenie.VHD: 

    
-- Quartus Prime VHDL Template
-- Signed Multiply
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nasobenie is
	generic
	(
		DATA_WIDTH : natural := 8
	);
	port 
	(
		a	   : in signed ((DATA_WIDTH-1) downto 0);
		b	   : in signed ((DATA_WIDTH-1) downto 0);
		q  : out signed ((2*DATA_WIDTH-1) downto 0)
	);
end entity;
architecture rtl of nasobenie is
begin
	q <= a * b;
end rtl;

    And now nasobenie_tb.vhd 

    library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity nasobenie_tb is
generic
  	(
  		DATA_WIDTH : natural := 4
  	);
end;
architecture bench of nasobenie_tb is
  component nasobenie
  	generic
  	(
  		DATA_WIDTH : natural := 2
  	);
  	port 
  	( 
  		a	   : in signed ((DATA_WIDTH-1) downto 0);
  		b	   : in signed ((DATA_WIDTH-1) downto 0);
  		q  : out signed ((2*DATA_WIDTH-1) downto 0)
  	);
  end component;
  signal a: signed ((DATA_WIDTH-1) downto 0);
  signal b: signed ((DATA_WIDTH-1) downto 0);
  signal q: signed ((2*DATA_WIDTH-1) downto 0) ;
begin
  -- Vlozenie hodnot pre parameter generic !!
  uut: nasobenie generic map ( DATA_WIDTH => DATA_WIDTH )
                          port map ( a          => a,
                                     b          => b,
                                     q     => q );
  stimulus: process
  begin
 a <= "00";
   b <= "00";
   wait for 10 ns;
    a <= "00";
   b <= "01";
   wait for 10 ns;
	a <= "00";
   b <= "10";
   wait for 10 ns;
	a <= "00";
   b <= "11";
   wait for 10 ns;
 a <= "01";
   b <= "00";
   wait for 10 ns;
	 a <= "01";
   b <= "01";
   wait for 10 ns;
a <= "01";
   b <= "10";
   wait for 10 ns;
	a <= "01";
   b <= "11";
   wait for 10 ns;
 a <= "10";
   b <= "00";
   wait for 10 ns;
	a <= "10";
   b <= "01";
   wait for 10 ns; 
	a <= "10";
   b <= "10";
   wait for 10 ns;
	a <= "10";
   b <= "11";
   wait for 10 ns;
 a <= "11";
   b <= "00";
   wait for 10 ns;
	a <= "11";
   b <= "01";
   wait for 10 ns;
	a <= "11";
   b <= "10";
   wait for 10 ns;
	a <= "11";
   b <= "11";
   wait for 10 ns;
	end process; --koniec opisu procesov
 end bench; --koniec opisu architektury tb
configuration cfg_bench of nasobenie_tb is --konfiguracia test bench entity
   for bench --cyklus je prazdny, nema ziadnu specificku funkciu v nasom pripade
   end for; --koniec cyklu
end cfg_bench; --koniec opisu konfiguracie
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    The error you have posted doesnt appear to be for this code.

    I suggest deleting the configuration from the code.