Honored Contributor
Honored ContributorAgain, sorry for keeping posting and the possible wrong terminology.
Anyway - the VHDL compilation works fine. No errors there. Later (in the script) when it goes to place (Fitter?) everything it has an error saying that the pin AD_25 is already assigned to nCEO and cannot be assigned to iSW7. Here are the messages: Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning: Feature LogicLock incremental compilation is not available with your current license Info: Fitter is using the Classic Timing Analyzer Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use Info: Previous placement does not exist for 92 of 92 atoms in partition Top Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info: Fitter converted 3 user pins into dedicated programming pins Info: Pin ~ASDO~ is reserved at location G7 Info: Pin ~nCSO~ is reserved at location K9 Info: Pin ~LVDS195p/nCEO~ is reserved at location AD25 Error: Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1) Info: Pin iSW[7] is assigned to pin location Pin_AD25 (IOC_X95_Y2_N1) Info: Pin ~LVDS195p/nCEO~ is assigned to pin location Pin_AD25 (IOC_X95_Y2_N1) Error: Can't fit design in device Billy
