Dual Port RAM acces in VHDL

I now solved this issue.

The problem was the addresses were assigned to late and the data from memory was assigned to the wrong port.

By introducing a state to "burn a clock cycle" between the setup_addr states and the read states makes the design work.

Now all the values are read correctly and the output port show the correct signals.

I thought it is possible to read data one clock cycle after applying the address, but obviously that is not correct.

is it possible to avoid this extra state by using somekind of wait statement? What is the best way to do this?

Cheers

Tim

(now my weekend will be much nicer ;))