DSP usage issue with arria10

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At first glance, I cant really understand why. It could just be a compiler bug with inference ie. you're not quite using the template expected. have you tried using separate intermediate signal outside of the clock process for the multiplication and addition, with only the final register in the process? Have you tried using intermediate variables instead?

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I did. Same behavior with this piece of code:

  abcd <= (a * b) + (c * d);
  efgh <= (e * f) + (g * h);
  abcdefgh <= abcd + efgh;
  dataout <= abcdefgh_reg;
  p_register : process(clk)
  begin
    if rising_edge(clk) then
      abcdefgh_reg <= abcdefgh;
    end if;
  end process p_register;