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Altera_Forum
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18 years ago

DSP Builder Error in Runnig

hi folks, this is my first topic here and i was really stuck in this so please help me the problem started by having a DDC example from the Altera website and wanted to check it on my ...
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Altera_Forum
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18 years ago

7.1 completely changed its simulation library and clocking schemes. Typically you now define your system clock rate with a Clock block. Set its rate to 'clock1' as your defined matlab variable. Name the clock block something. 'Clk1' will avoid confusion. Then define the sampling rates of all your inputs by setting their input clock rate to 'Clk1'. Note you need to use the Clock block name, not the Matlab variable.