Driver and associated documentation to interface to PCIe Hard IP for Cyclone V

Unfortunately, Linux drivers aren’t going to be helpful as we’re gearing the design for a Win10 OS DoD customer. Do you know of a Win10 driver example?

Here are some additional questions we have:

PCIe Hard IP

* I believe that the Cyclone PCIe Hard IP supports either Dynamic Clock Recovery (DCR) or the use of a 100 MHz Reference Clock. Is this a correct understanding?

* From what I’ve been told, OpenVPX is moving away from the use of a Ref Clock.

* Are there any issues with DCR operation from either a Tx or Rx standpoint?

* What option does Altera recommend for ease of use?

* If a Ref Clock is used, is there any limitation or restriction on which Ref Clock pin on the FPGA Transceiver banks the clock is attached to?

Software Driver & DMA

* I can’t find any information regarding the software driver Intel/Altera uses to communicate with the PCIe Hard IP in the Cyclone V.

* Does Altera have such a driver?

* If so, where is it located so I can download it from their website?

* How is DMA enabled in the Hard IP and how is it configured?

* Are there Rx/Tx FIFOs in the Hard IP and does the user have control over FIFO Almost Full or Almost Empty signaling?

Platform Designer

* I’m interested in taking training courses on Creating PCI Express Links Using FPGAs (IPCIE) <

https://www.intel.com/content/www/us/en/programmable/support/training/course/ipcie.html> and Advanced Qsys System Integration Tool Methodologies (IQSYS102) <https://www.intel.com/content/www/us/en/programmable/support/training/course/iqsys102.html

> but both are showing no classes are scheduled.

* Any possibility of getting the course materials for these so I can self-study?

FPGA Configuration Options

* Looking for a recommendation of the latest best practices on configuration.

* In the past, I’ve always used single-bit serial devices (EPCS type) for FPGA configuration using AS configuration

* I see that there are 3rd party four-bit serial devices (EPCQ type) now.

* I also see the Flash/Max example on Cyclone V DVK I purchased that use a 16b parallel flash in conjunction with a MAX V

* Do you or Intel/Altera have a recommendation for FPGA configuration? I’d like to keep the configuration as simple and straightforward as possible. We have no issues with time for configuration (unless addl constraints are required for the use of PCIe Hard IP), so serial single-bit is fine unless you recommend otherwise.

ToddW