Forum Discussion
MEIYAN_L_Intel
Frequent Contributor
6 years agoHi,
It seems like the output for pll_locked to output_a is not a timing path.
CDC rules only show violation for timing paths.
Thanks
MOliv45
New Contributor
6 years agoHi,
Indeed. There is an internal request at intel to discuss if this port should be timed or not.
I believe it should. In one way or the other the DRC check has to be able to detect a missing synchronizer from an IP port, right?
Cheers.