New Contributor
Regular ContributorHello,
I don't quite get what your problem is. Can you please elaborate so I can help you further?
Thanks.
New ContributorFPGA:1SG280LU2F50E2LG Quartus II 20.1
output TBE0n,
VCCH_GXB, VCCR_GXB and VCCT_GXB are connected to GND
Pin Planner，TBE0n->AF16(any Pin in the 3.0v Bank 6A, 6C, 7A or 7C)，I/O Standard is selected 3.0-V LVCOMS(or 3.0-V LVTTL )
The project is compiled successfully
When downloading the sof file to 9%, the following error occurs
Device has stopped receiving configuration data
Error message received from device: Detected internal error. Contact Intel Applications for further assistance. (subcode 0x002D, Info 0x00000000, Location 0x0010800)
Operation failed Pin Planner，
but
TBE0n->XX(the pin is not in the in the 3.0v Bank 6A, 6C, 7A or 7C)，I/O Standard is selected 1.8v. The project is compiled successfully and the the sof file is downloaded successfully.
Regular ContributorHello,
The error may come up due to a PLL calibration failure of the input reference clocks resulting in failure at about 23% during the programming stage.
Please refer to this link: https://www.intel.com/content/www/us/en/support/programmable/articles/000075102.html
Thank you.
Regular ContributorWe do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
New ContributorAdminT,
I have same error code as fu_aolin: subcode 0x002D, Info 0x00000000, Location 0x0010800.
You replied with the link to 000075102.html but the location is different: 0x00019000.
Did you make a mistake, or the location does not matter for this error?
