Forum Discussion
Altera_Forum
Honored Contributor
9 years agoI had a similar problem, albeit in a different context. I did the exercise in the University Program tutorial introduction to the altera qsys system integration tool (https://www.altera.com/support/training/university/materials-tutorials.html) and everything went fine until I started the Monitor Program, loaded the generated system onto the FPGA and compiled the assembly program. But then, upon trying action Load, to load the .elf file, I got the following:
Using cable "DE-SoC ", device 2, instance 0x00
Resetting and pausing target processor: FAILED
Leaving target processor paused
The culprit was the fact that I had forgot to import the DE1_SoC.qsf pin assignments into lights.qsf, before compiling the generated system in Quartus...