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Altera_Forum
Honored Contributor
15 years agoIn my case the change was in the top-level file that hooks everything together. The real culprit was that I tied the Nios reset to a reset output that drove the clock generator chip that was providing the base clock to the FPGA. So when the development tools tried to reset the Nios processor it also reset the clock generator chip, which temporarily incapacitated the FPGA. Oops.