Honored Contributor
Honored ContributorAccording to my experience, PLL problems with Cyclone II are mainly caused by interferences at the PLL analog powersupply. Cyclone III and it's sucessors have been provided with internal VCCA voltage regulators to overcome this weakness. Ground bounce respectively simultaneous switching noise (SSN) is an important factor in causing PLL unlock. It's particularly weird with large PQFP package due to the large lead frame and low ground pin count.
A customer had a design with a processor interface, where the 32-Bit data bus had to bet cut back to 16-Bit to achieve regular PLL operation. PLL unlock could be brought up by reading 32-Bit data from FPGA to the processor. Apparently the SSN caused by driving the bus was too much for the PLL. I wasn't involved in the PCB design, but as far as I remember, it's observing good engineering practice with separate VCCA decoupling. An inappropriately bypassed "ringing" linear 1.2V regulator also caused PLL problems, but these could be easily eliminated. With another design, where external interferences additionally have been disturbing PLL operation, disabling the PLL and changing the design to a high frequency crystal oscillator seemed to be the only reliable method to make it work. Today, the problem has become legacy, because new designs are always based on Cyclone III or above.
