Honored Contributor
Honored ContributorHi Pete,
--- Quote Start --- I suspect some sort of data crosstalk inside the device. This seems a weird idea (after all my years designing with CPLDs) so I am open to any suggestions :) --- Quote End --- How about testing that theory? Create a design with a large number of pseudo-random binary sequence (PRBS) generators and checkers. The generators can send PRBS data through varying depths of pipeline registers to use resources on the device. Then at the checkers, each receiver PRBS would be loaded from each transmit PRBS, and would then count errors in the received streams. You do this by xor'ing the PRBS from the transmitter with the PRBS at the receiver (that was previously loaded from the transmit stream); if there are any bits different, the xor result will have bits set. If you get errors, then your hypothesis would be confirmed; you still might have clock errors, but at least this is an all-internal test that will assist in debug. There are Avalon cores for PRBS generation and checking, you could try those, or if they give you trouble, use the PRBS generator in here: http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip) There's another component not in there called 'count_ones.vhd' that will count the error bits in each xor result, and then accumulate the results ... see the attached VHDL ... Cheers, Dave
