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After looking into the project source code and instructables (
http://www.oreganosystems.at/download/mc8051_cyclone_nios_designflow.pdf), I gather that in the Oregano 8051 design configurations are not to used for synthesis.
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I thought the memory interfaces were defined by configurations, i.e., generic memory for simulation and then device-specific memory for synthesis. Then again, perhaps they did something "special" to support the DE2 board.
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Also, most of the synthesis process (at least everything that is vendor-agnostic) is done with Synplify Pro.
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I know I tested the core with Modelsim, but I thought I synthesized the DE2 design with Quartus ...
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Seems to support the general idea that configurations are not much used for synthesis...
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I think its more that Quartus lacks the synthesis support (along with several other standard language features), so as the end-users we're forced to work within the constraints of the vendor tool :)
You could try Mentor's tools, eg., Precision or Leonardo, generate an EDIF netlist, and then synthesize that.
Cheers,
Dave
Honored Contributor
