Does Quartus support SV Alias Keyword?

This should be simple one to answer:

Why doesn't this code work?

logic lhs;
logic rhs;
alias lhs = rhs;

Quartus just yells at me in red times new roman...

Error (10170): Verilog HDL syntax error at top_level.sv(77) near text "alias"; expecting "endmodule"

Thanks in advance for your time.