Does Quartus PRO supports 'HDL convert to bsf file' function？

Yes, thanks for the tip. What I'm doing is keeping a dummy project open in the Standard edition, and that allows me to generate .bsf symbols for my project in the Pro edition. I just load the files I need to create in standard, and update them from Pro. I keep two File Explorer windows open so I can slide some of the .bsf symbol files created in Standard edition over to the correct directory.

There is great misunderstanding by Intel when it comes to schematic level/block level design entry for FPGAs. Intel must be thinking we're using "AND" gate symbols or something like that out of their old library. That's not what we're doing! What engineers are doing is building complex modules in Verilog or VHDL. Once that's debugged, they convert the module to a block diagram, just like the Intel IP does now.

The reason Engineers do this, is because the complexity of the module interconnections is made simple. For example, consider a systolic matrix multiplier comprised of many sub-module ALU units. It's just easier to connect these ALU modules into a full-blown matrix multiplier using the block symbol approach. Once that is done, we convert the top-level schematic back to Verilog for simulation.

Block diagrams that are generated automatically from your Verilog code is NO replacement for the block diagram structure created by the designer. This is another misconception.

I DO see why Intel doesn't want to support the old .bsf symbol creation process in Pro. But just taking it out is the wrong action. Intel should create a way to create .bsf files from the IP configurator platform and allow engineers to drop associated .sdc files to be associated with those symbols. In other words, Intel CAN make the .bsf symbol generation compliant to their new directory structure under Pro. Apparently, Intel doesn't want to.

If Intel was thinking of electrical engineers, and how EE's might pollenate new applications for Intel devices, then Intel should provide an easy method to encrypt our Verilog during the symbol creation process. (IEEE standard made easy). (It's another problem Intel doesn't understand .... Electrical Engineers end up going into the software profession because software can easily be developed and licensed. On the other hand, electrical engineers are being stripped of any such opportunities (and I hate to say it .... by Intel).

Lastly, Xilinx Vivado supports block diagrams throughout the entire design process. There is no limiting the Engineers ability to use block symbols. But if Quartus can solve this simple issue, make the schematic capture software a bit better, then Intel would really have a leg up over Xilinx. It's a shame. So, until Intel realizes that this decision was very poorly made, I'll need to work between the standard and Pro editions to get the job done! Ooouch!!!

Look, some of these feature deprecations are being decided because of other factors, like not having control over the schematic software. Fix that!

Regards,

Eric Olsen