Does Quartus II 12.1 support Systemverilog 2005 in the following form?

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PS. Quartus (and Vivado) has always picked specific parts of VHDL, Verilog and System verilog that they support. They never claim have full language support.

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Yes, you are quite right. I also found what it described in handbook is like this:

http://www.alteraforum.com/forum/attachment.php?attachmentid=11942&stc=1

I just can't find the accurate description of the way to use generate construct.

Thank you very much!