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JDe_S4's avatar
JDe_S4
Icon for New Contributor rankNew Contributor
7 years ago

Does Quartus 18.0 support the VHDL 2008 'ELEMENT attribute?

I am using the VHDL 'ELEMENT attribute to determine the range of an element in an array. ReadRegisterData: process (REG_CLK) is begin if (rising_edge(REG_CLK)) then i_RegReadD...
Tricky's avatar
Tricky
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

There is an easy workaround for this (that works in '93):

-- If you know the array always contains index 0 (or some other fixed number):
i_RegReadData(i_DAC_CodeWordMaskReg(0)'RANGE)
 
-- You dont know the indeces
i_RegReadData(i_DAC_CodeWordMaskReg(i_DAC_CodeWordMaskReg'low)'RANGE)