Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThank you guys, your replies helped me a lot! I implemented the approach that kaz suggested using a lpm_mult and I wonder how many latency clock cycles I should choose. The clock frequency is 178.2 MHz, dataa is 15-bit long, datab is 10-bit long and the output is then 25-bit long, so I am using a built-in 18x18 DSP. I have been looking for some information about the latency but I still did not fin anything about how to choose the optimal latency. Depending on the latency I will need to delay some other signals accordingly, so I really need to know exactly what I am doing :P So how could I find out the number of cycles that are necessary to multiply two variables? Thank you again!