Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi
while I'm not into Verilog (doing VHDL), I think the basic approach is identical... You need to have some "lookup" to define which segments need to be activated depending on the number to be shown. In VHDL this might be a case seg1 is when "1" => "0000110" when "2" => "1011011" ... The "problem" is a direct conversion of the byte of the number to the seven segement will show the values as hexadecimals... Otherwise - if e.g. "13" should be "1" "3" and not "0" "D" you first have to convert hexadecimals to binary coded decimals...