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Altera_Forum
Honored Contributor
Honored ContributorDisplay of amount of Block RAM used for a SC_FIFO missing
Hallo, I used Quartus 16.1.203 to compile a design where I used a FIFO IP which is, I assume is synthesised/built as a RAM. The compilation is successful. But in the summary I do not see...
Altera_ForumHonored Contributor
Honored ContributorYes. I let Quartus decide (chose auto in Megawizard).
The resource utilization for this fifo (logic unit) is completely empty as you can see in the image.
