direct DDR communication via VHDL/Verilog

Hello everyone,

Coming back to the subject!

I managed to advance quite well in my path to RTL library to DDR communication. I now have a RTL component that will be encapsulated into an OpenCL library. This component has one pointer and one data on its input part. For the ouput part, it exposes an Avalon MM master interface that will communicate with the BSP bus (theoretically).

But I ran into some curious bug when using the OpenCL compiler:

aoc device/kernel.test.cl -o bin/ddr_w_lib.test.aocx -I lib_src -L lib_src -l ddr_w_lib.aoclib -v -report -fpc -fp-relaxed
Resolving library filenames to full paths
  lib_path = lib_src
  lib_file = ddr_w_lib.aoclib
Resolved ddr_w_lib.aoclib to /.../ddr_w_lib.aoclib
   lib_path = .
aoc: Environment checks are completed successfully.
aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/
You are now compiling the full flow!!
aoc: Selected default target board xpressgxa10_lp1150_v1_ultra_ddr4
aoc: Running OpenCL parser....
error: Unexpected use of HDL library function(s) (possibly due to taking the address of the function)!
error: Unexpected use of HDL library function(s) (possibly due to taking the address of the function)!
2 errors generated.
Error: OpenCL parser FAILED.
Refer to ddr_w_lib.test/kernel_test.log for details.

There is nothing more to show in kernel_test.log.

Here are my OpenCL kernel and the declaration of my library:

__attribute__((max_global_work_dim(0)))
kernel void test_lib (__global ulong* restrict pointer, ulong data) {
       ddr_w_rtl(pointer, data);
}

You can see that my kernel will simply do one thing. It will write "data" to the DDR at the address "pointer".

Here is the declaration of my RTL library:

void ddr_w_rtl (__global ulong* pin, ulong din);

What is wrong here ? What does this strange error mean btw ?

I tried some hack found here (https://www.alteraforum.com/forum/showthread.php?t=57724). So my library definition changed for this:

void ddr_w_rtl (__global unsigned long long* pin, ulong din);

Here is the output of the compiler this time:

aoc device/kernel.test.cl -o bin/ddr_w_lib.test.aocx -I lib_src -L lib_src -l ddr_w_lib.aoclib -v -report -fpc -fp-relaxed
Resolving library filenames to full paths
  lib_path = lib_src
    lib_file = ddr_w_lib.aoclib
Resolved ddr_w_lib.aoclib to /home/bourgea/repo/fanna/device/rtl_lib/ddr_w_lib/lib_src/ddr_w_lib.aoclib
  lib_path = .
aoc: Environment checks are completed successfully.
aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/
You are now compiling the full flow!!
aoc: Selected default target board xpressgxa10_lp1150_v1_ultra_ddr4
aoc: Running OpenCL parser....
/home/bourgea/repo/fanna/device/rtl_lib/ddr_w_lib/device/kernel.test.cl:6:12: warning: incompatible pointer types passing '__attribute__((address_space(16776960))) ulong *restrict' (aka '__attribute__((address_space(16776960))) unsigned long *restrict') to parameter of type '__attribute__((address_space(16776960))) unsigned long long *'
        ddr_w_rtl(pin, din);
                  ^~~
lib_src/ddr_w_lib.h:1:46: note: passing argument to parameter 'pin' here
void ddr_w_rtl (__global unsigned long long* pin, ulong din);
                                             ^
/home/bourgea/repo/fanna/device/rtl_lib/ddr_w_lib/device/kernel.test.cl:6: Compiler Error: Wrong input type for HDL library function call <ddr_w_rtl> Operand# 1: Expected: pointer Actual: scalar
Error: OpenCL parser FAILED.
Refer to ddr_w_lib.test/kernel_test.log for details.

This time, I understand the first warning :)

But I don't get the error.

Is this trick the way to go ?

I attached my XML property file just in case the bugs is hidden in it.