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Few points that may help you both:
1. If you want to integrate you own RTL into OpenCL system you may want to simulate merged design. Looks like @haveidea wants to do this anyway. BTW I would not involve BSP into simulations yet. There are few CRA registers that you can set up to run kernels that do bus acecssees, etc. Global DDR memory is just an Avalon MM bus.
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Yep, that was of course in my mind. BSP simulation ? Looks awful :)
Actually, it seems that the interface my BSP gives is an Avalon-MM bridge, but if I understood well, this is transparent for the master part.
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2. Officially Intel/Altera do not support simulations of the OpenCL system. However, there is a way to get an Avalon master module and simulate the OpenCL system by running its kernel and bus accesses w/o BSP:
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I dit not get if your ":" refers to point 3. or if you missed a cut/paste?! Because simulating what is produced by the OpenCL compiler with my RTL inside would be interesting.
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3. Here is a command for you to try: qsys-generate kernel_system.qsys --simulation=VERILOG --testbench --testbench-simulation. Watch how all necessary the directories and files it will create. Use directory compare before and after command ;).
It will also generate the simulation model with BFMs and Avalon verification IP of Avalon bus. Thare is more information here
https://www.altera.com/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html. The master is there. Good place to start as well as Avalon manual.
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Currently, I do not us qsys to generate my kernel because I simply did not started the project. I'm still wondering if I can avoid using the Qsys GUI.
I am currently digging into the verification IP. I try to understand how the entire designs are connected. It requires some skills to get through all the procedures. The API to be found in ug_avalon_verification_ip.pdf to drive the BFMs is not complete or higher level instruction are created along the way which obfuscate a little bit my understanding. But I'm working on it.
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4. This simulation model will use BFMs instead of DDR which is probably enough for basic RTL simulation. @b_alban guess what? You are not the first one to seek these answers, so search a bit more the next time. You can find a way of handling BFM one write and one read at a time at this thread:
https://www.alteraforum.com/forum/showthread.php?t=32952&highlight=david+hawkins+%26lt%3bdwh%40ovro.caltech.edu%26gt%3b. If you will need burst transcations to BFMs please contact me off-line. Our company has a solution and we have successfully simulated OpenCL systems.
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That I already guessed but finding up-to-date information is tough because there is a high dependancy wrt tool version. And Quartus/Qsys/Altera FPGA architecture changes quite a lot recently!
I agree, BFM simulation is largely enough.
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And @ b_alban, if you want to share the bus with the vendor BSP bus to DDRx you likely will need an arbiter that interfaces to "complicated stuff".
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The arbitration network is already shipped into the BSP. It resolve all the load/store (cf. intel FPGA SDK for OpenCL Programming guide page 131). I'm wondering now if the bridge connects to the arbitration network and how can we share the bridge between kernel Avalon-MM interfaces ...
Anyway, thanks for the help and tips !
Honored Contributor
