direct DDR communication via VHDL/Verilog

Few points that may help you both:

1. If you want to integrate you own RTL into OpenCL system you may want to simulate merged design. Looks like @haveidea wants to do this anyway. BTW I would not involve BSP into simulations yet. There are few CRA registers that you can set up to run kernels that do bus acecssees, etc. Global DDR memory is just an Avalon MM bus.

2. Officially Intel/Altera do not support simulations of the OpenCL system. However, there is a way to get an Avalon master module and simulate the OpenCL system by running its kernel and bus accesses w/o BSP:

3. Here is a command for you to try: qsys-generate kernel_system.qsys --simulation=VERILOG --testbench --testbench-simulation. Watch how all necessary the directories and files it will create. Use directory compare before and after command ;).

It will also generate the simulation model with BFMs and Avalon verification IP of Avalon bus. Thare is more information here https://www.altera.com/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html. The master is there. Good plave to start as well as Avalon manual.

4. This simulation model will use BFMs instead of DDR which is probably enough for basic RTL simulation. @b_alban guess what? You are not the first one to seek these answers, so search a bit more the next time. You can find a way of handling BFM one write and one read at a time at this thread: https://www.alteraforum.com/forum/showthread.php?t=32952&highlight=david+hawkins+%26lt%3bdwh%40ovro.caltech.edu%26gt%3b. If you will need burst transcations to BFMs please contact me off-line. Our company has a solution and we have successfully simulated OpenCL systems.

And @ b_alban, if you want to share the bus with the vendor BSP bus to DDRx you likely will need an arbiter that interfaces to "complicated stuff". You may have to write it or hire someone. Good luck!