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Altera_Forum's avatar
Altera_Forum
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9 years ago

Different simulate result from quartus and modelsim

I wrote a verilog program as follow UD_Cnt(CLK,UD_counter) is a Up-down counter module, CPS_PWM(CLK,Cx) is a PWM module, containing multiple UD_Cnt module with different initial value。 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Don't you need to pass two parameters? If so, these lines are wrong:

UD_Cnt# (257) UDxx(CLK_150M,CC);

UD_Cnt# (259) UDxx(CLK,Cx);

You're not including the direction parameter.

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Not wrong. If you don't supply the parameter in the module instantiation it will use the default value supplied in the parameter statement.

However, in the UD_Cnt module in a couple of IF statements you use the bitwise AND operator (&) instead of the logical AND (&&) operator to combine conditionals.