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Honored Contributor
Honored ContributorDifferent simulate result from quartus and modelsim
I wrote a verilog program as follow UD_Cnt(CLK,UD_counter) is a Up-down counter module, CPS_PWM(CLK,Cx) is a PWM module, containing multiple UD_Cnt module with different initial value。 ...
Altera_ForumHonored Contributor
Honored ContributorDon't you need to pass two parameters? If so, these lines are wrong:
UD_Cnt# (257) UDxx(CLK_150M,CC); UD_Cnt# (259) UDxx(CLK,Cx); You're not including the direction parameter.
