New Contributor
Super ContributorYou probably looking at the Pro version document, Cyclone 10 LP is supported. Check the document link below:
https://www.intel.com/content/www/us/en/docs/programmable/683084/current/allow-register-merging.html
You can double check in the Assignment > Setting > Compiler Settings > Advanced Setting (synthesis). Search for Allow Register Merging and check that it is set as ON.
Best Regards,
Richard Tan
New ContributorI double checked it as you suggested and Quartus tells me that it is ON.
But still, I got the same Analysis & Synthesis result as i run Quartus on a Windows machine and set the feature OFF.
In the end the Design does not fit into the FPGA and Fitter fails (on the Linux VM, un Windows it still works fine).
Any other suggestions ?
