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pdewanga's avatar
pdewanga
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Determining the Max payload size encoding

Hi Quartus Support Team, Attaching the screen-shot from the "L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SRIOV) Intel® FPGA IP for PCI Express* User Guide" Table 43. What...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,

    Thanks for correcting me, my apologize for misunderstanding the question.

    For your information the spec is not owned by intel, it is a general spec that all PCIe IP need to follow.

    You can get the detail in "PCI Express® Base Specification" in the web.

    For your question, I do help to printscreen it to you.

    Max rd req size

    Max payload size

    Hope this answer your question, Let me know if this is helpful to you.

    Regards,
    Wincent_Intel

pdewanga's avatar
pdewanga
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

The text you copy and pasted is from user guide, that we have gone through.

There is no issue of configuration. I just want to use this two following signal for our design.

[5:3] Max rd req size

[2:0] Max payload size

Actual question to make you more clear-

question:- Please share more details about the encoded value of this signals ( [5:3] Max rd req size [2:0] Max payload size ). What does each state means ?

Please don't copy paste the user guide content, We have gone through that but nothing is listed there properly.

Thanks

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Thanks for correcting me, my apologize for misunderstanding the question.

For your information the spec is not owned by intel, it is a general spec that all PCIe IP need to follow.

You can get the detail in "PCI Express® Base Specification" in the web.

For your question, I do help to printscreen it to you.

Max rd req size

Max payload size

Hope this answer your question, Let me know if this is helpful to you.

Regards,
Wincent_Intel