Design Verilog coding for 8-bit accumulator

Here is the QAR file. I have provided a full picture and requirements in the picture also.

if there is still can't find the fulladd, here is the code for it:

module fulladd(a, b, cin, s, cout);
input a, b, cin;
output s, cout;

assign s = a ^ b ^ cin;
assign cout = ((a ^ b) & cin) | (a & b);
endmodule

I didn't do any testbench for this design. But this is the waveform I got.