Design Unit Not Found

Hello,

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Does vlog work on vht test bench files normally?

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No. .vht stands for VHDL test bench file while vlog command compiles Verilog source code and SystemVerilog source codes. Hence it will not work.

You should try following :

1. In Quartus, Go to Assignments -> Settings... -> EDA Tool Settings -> Simulation.
   In that select 'Verilog' under 'Format for Output Netlist'.

2. In Quartus, Go to Processing -> Start... -> Start Test Bench Template Writer
   This should now create dac_top.vt file in same folder in which dac_top.vht file was being created before.

3. Now try following command: vlog -reportprogress 300 D:/Users/

We would like to know what happens with this.

Thank you,

Bhaumik