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Hello,
Thank you for your kind words. Whenever I am in trouble, someone on this forum helps me, so I am just trying do same. And I am glad that it is helpful to you.
Anyway, let get back to our topic.
vlog command compiles Verilog source code and SystemVerilog extensions into a specified working library while vsim command invokes the VSIM simulator. Consider tb_test is your test bench TOP file. In this case, first you need to compile this using vlog command. ( In the same way you are compiling your dac_top.v and other files.) Then you can use following command : vsim -L altera_mf_ver work.tb_test.
Let us know whether it works or not.
Cheers,
Bhaumik
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Bhaumik, I think I am getting closer. Thank you.
I decided to create a TestBench file. To do so, I used:
Processing -> Start... -> Start Test Bench Template Writer
This gave me a .vht file titled dac_top.vht. Next, I went to:
Assignments -> Settings... -> EDA Tool Settings -> Simulation -> Test Benches...
I created a new test bench titled 'dac_top_tb', and Top level module in test bench = 'dac_top_tb'. I added this file to the project as well.
My .do file was automatically updated with a new vsim line, which includes all of the proper libraries:
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L rtl_work -L work -voptargs="+acc" dac_top_tb
add wave *
view structure
view signals
run -all
However, now I am getting a very similar answer to before- however, I don't know what library my test bench is in?
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L rtl_work -L work -voptargs=""+acc"" dac_top_tb# Start time: 16:16:42 on Mar 22,2016# ** Error: (vsim-3170) Could not find 'D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/rtl_work.dac_top_tb'.# # Error loading design
Can you see what I am doing wrong?
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