Design Unit Not Found

Hello,

Thank you for your kind words. Whenever I am in trouble, someone on this forum helps me, so I am just trying do same. And I am glad that it is helpful to you.

Anyway, let get back to our topic.

vlog command compiles Verilog source code and SystemVerilog extensions into a specified working library while vsim command invokes the VSIM simulator. Consider tb_test is your test bench TOP file. In this case, first you need to compile this using vlog command. ( In the same way you are compiling your dac_top.v and other files.) Then you can use following command : vsim -L altera_mf_ver work.tb_test.

Let us know whether it works or not.

Cheers,

Bhaumik