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This is usually a result of the designer using the ram blocks inefficiently. If each of these takes a ram block, thats 9k bits per ram. And even the largest S3 part only has 1000 M9Ks. From your description, Im guessing you are using the rams highly inefficiently.
Without any code, it's difficult to see what you're doing.
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after several tries, I got my design to fit on Stratix III but the fitter summary shows that the number of block memory bits used is zero!! Although I am using the following verilog code for each ROM block:
module Block1(addr, clk, out);
input [3:0] addr;
input clk;
output [31:0] out;
(* romstyle = "M9K" *) reg [31:0] out;
always @(posedge clk)
// assign values to out using case statement
endmodule
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