Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Design requires too many ram resources to fit in the selected device

Hello, I have a design on verilog code that contains many modules. 4 modules represent ROM blocks (16 x 32-bit) that has 4-bit address, 32-bit data out. So each ROM block is 512 bits with a t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

module block1(addr, clk, out);

input [3:0] addr;

input clk;

output [31:0] out;

(* romstyle = "M9K" *) reg [31:0] out;

// assigning values using always block and case statement

endmodule

this is the code for the one of the ROM blocks.