Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Design requires too many ram resources to fit in the selected device

Hello, I have a design on verilog code that contains many modules. 4 modules represent ROM blocks (16 x 32-bit) that has 4-bit address, 32-bit data out. So each ROM block is 512 bits with a t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Review the fitter resource utilization reports. What you'll possibly find is that each of your 16x32 ROM are consuming (1) M9K block, using (4) blocks with capacity >32,000 bits even though you're only using 2,048 of them. i.e. your design doesn't map efficiently to the available hardware resources and you may need to rethink some things.

http://www.altera.com/literature/hb/cyc3/cyc3_ciii51004.pdf