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Altera_Forum's avatar
Altera_Forum
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11 years ago

Design requires too many ram resources to fit in the selected device

Hello, I have a design on verilog code that contains many modules. 4 modules represent ROM blocks (16 x 32-bit) that has 4-bit address, 32-bit data out. So each ROM block is 512 bits with a t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

This is usually a result of the designer using the ram blocks inefficiently. If each of these takes a ram block, thats 9k bits per ram. And even the largest S3 part only has 1000 M9Ks. From your description, Im guessing you are using the rams highly inefficiently.

Without any code, it's difficult to see what you're doing.