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Altera_Forum
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10 years ago

Design Flow Tips for Obtaining High Fmax as FPGA Gets Full

I just completed an Arria V design whose individual logic blocks achieved about 177MHz performance, but when instantiated 6 times obtained only about 120MHz performance in a chip that is about 70% fu...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Are the failing paths entry and exits from Rams or DSPs? with plenty of room, the fitter can often put the logic right next to the ram/dsp, but when it gets full, these paths can get stretched because the rams and DSPs cannot be moved. Add extra pipeline registers to the input and output of rams and it gives the fitter a break with simple register - regsiter routing without having to worry about LUTs in between.

Did you also set your false paths and multi-cycle paths in the SDC file?